1. Field of the Invention
The invention is directed to the mass production of semiconductor devices. The invention is more particularly directed to the problem of processing lots of wafers sharing one or more common defects and to resolving those defects.
2. Cross Reference to Related Publications
The following publications are cited here for purposes of reference:
(1) S. Kaplan and L. Karklin, xe2x80x9cCalibration of Lithography Simulator by Using Substitute Patterns,xe2x80x9d Proceedings on Optical/Laser Microlithography VI, SPIE 1927, pp. 847-858, 1993.
(2) C. Mack and E. Charrier, xe2x80x9cYield Modeling for Photolithography,xe2x80x9d Proceedings of OCG Microlithography Seminar, pp. 171-182, 1994.
(3) TMA DEPICT, Two-Dimensional Process Simulation Program for Deposition, Etching, and Photolithography, version 3.0, Technology Modeling Associates, Inc., Palo Alto, Calif., 1993.
(4) Mandel, J, The Statistical Analysis of Experimental Data, Chapter 12, Wiley, N.Y., 1964.
(5) Z. Krivokapic and W. D. Heavlin, xe2x80x9cPredicting Manufacturing Variabilities for Deep Micron Technologies: Integration of Process, Device, and Statistical Simulations,xe2x80x9d in Simulation of Semiconductor Devices and Processes, 5, S Selberherr, H Stippel and E Strasser, eds, pp. 229-232, Springer-Verlag, N.Y., 1993.
(6) W. D. Heavlin and G. P. Finnegan, xe2x80x9cDual Space Algorithms for Designing Space-filling Experiments,xe2x80x9d Interface 1994, Research Triangle, North Carolina, June 1994.
(7) B. D. Ripley, Spatial Statistics, pp. 44-75, Wiley, N.Y., 1981.
(8) A. B. Owen, xe2x80x9cControlling Correlations in Latin Hypercube Samples,xe2x80x9d Journal of the American Statistical Association, Vol. 89, No. 428, pp.1517-1522, December 1994.
(9) W. D. Heavlin, xe2x80x9cVariance Components and Computer Experiments,xe2x80x9d 1994 ASA Proceedings, Section on Physical and Engineering Sciences, Toronto, August 1994.
(10) A. R. Neureuther and F. H. Dill, xe2x80x9cPhotoresist Modeling and Device Fabrication Applications,xe2x80x9d Optical and Acoustical Microelectronics, pp. 223-247, Polytechnic Press, New York, 1974.
(11) F. H. Dill, J. A. Tuttle, A. R. Neureuther, xe2x80x9cModeling Positive Photoresist,xe2x80x9d Proceedings, Kodak Microelectronics Seminar, pp. 24-31, 1974.
(12) C. Mac, xe2x80x9cDevelopment of Positive Photoresists,xe2x80x9d Journal of the Electrochemical Society, Vol. 134, January 1987.
(13) M. Stein, xe2x80x9cLarge Sample Properties of Simulations using Latin Hypercube Sampling,xe2x80x9d Technometrics, Vol. 29, No. 2, pp. 143-151, May 1987.
(14) M. D. McKay and R. J. Beckman, xe2x80x9cUsing Variance to Identify Important Inputs,xe2x80x9d 1994 ASA Proceedings, Section on Physical and Engineering Sciences, Toronto, August 1994.
(15) William D. Heavlin and Luigi Capodieci, xe2x80x9cCalibration and Computer Experiments,xe2x80x9d 1997 American Statistical Association Proceedings, Section on Physical and Engineering Sciences, Anaheim, August 1997 (scheduled for publication Summer 1998), pp. 58-63.
(16) Heavlin, W. D., xe2x80x9cStatistically Based Process Windows, 1998 American Statistical Association Proceedings, Section on Physical and Engineering Sciences, pp. 216-221.
(17) Krivokapic, Z., Heavlin, W. D., and Kyser, D., U.S. Pat. No. 5,646,870 issued Jul. 8, 1997, entitled xe2x80x9cMethod for Setting and Adjusting Process Parameters to Maintain Acceptable Critical Dimensions Across Each Die of Mass-Produced Semiconductor Wafers.xe2x80x9d
(18) Krivokapic, Z., Heavlin, W. D., and Kyser, D., U.S. Pat. No. 5,655,110 issued Aug. 5, 1997, entitled xe2x80x9cMethod For Setting And Adjusting Process Parameters to Maintain Acceptable Critical Dimensions Across Each Die of Mass-produced Semiconductor Wafers.xe2x80x9d
Each of the aforementioned publications is hereby incorporated by reference.
3. Description of the Related Art
Modern, high-density, integrated circuit (IC) devices are typically mass-produced with large numbers of critically-dimensioned features. In manufacturing, it is desirable to maintain the respective critical dimensions of each die within a plurality of mass-produced IC wafers constrained to certain respective values in order to assure desired operating speeds and operational characteristics of the produced IC.
Each feature on each IC die in a mass-produced wafer is the product of a succession of many process steps. Each process step is controlled by a combination of variable process parameters.
Different combinations of variations in process parameter can occur on a random basis across the numerous process steps of a mass-production line, on a die-by-die basis. This introduces noise into the uniformity of the product outflow of the production line. Sometimes a specific combination of process parameter deviations is relatively innocuous, sometimes it is not. It all depends on which process parameters are deviated for a given IC die and how their respective process steps interrelate to establish critical dimensions on that given die.
One example of such multiple, interrelated process steps that may be useful in understanding the interaction of factors in the present application, are those typically employed to define a pattern of conductive lines deposited across an insulator of an IC chip.
First, a dielectric layer of a generally non-planar form is created across the wafer. Such a non-planar dielectric layer may constitute the combined gate oxide and field oxide of a CMOS device. The non-planarity of the dielectric layer may alternatively be attributed to the non-planarity of underlying trenches, steps, mesas or other topographic features of the chip.
Next, a polysilicon or other conductive layer is deposited conformably on top of the dielectric layer. An anti-reflective coating (ARC) may be optionally deposited on the conductive layer to reduce undesired reflections in a following exposure step.
The deposition of the conductive layer and optional ARC layer is followed by a spinning-on or other deposition of a photoresist (PR) layer. The PR layer may or may not be planarized depending on process specifics.
The photoresist-coated wafer is then positioned within a stepper by an alignment mechanism. Tiled areas of the photoresist (PR) are successively exposed to a stepped pattern of resist-modifying radiation. After the step-wise exposure, the photoresist is xe2x80x9cdevelopedxe2x80x9d by, for example, soft baking the wafer to induce cross-polymerization in the photoresist material and by subsequently dissolving away non-hardened portions of the photoresist with a specific solvent. The developed photoresist defines an etch mask.
The developed wafer is next etched, for example in a plasma etch chamber, so as to transfer the hardened image in the photoresist to the conductive layer. This produces a corresponding pattern of lines in the conductive (e.g., doped polysilicon) layer.
The photoresist mask is stripped off, or kept depending on process specifics, and further process steps follow. One example of a further process step is the selective implant of dopants into exposed semiconductor regions so as to create self-aligned source and drain regions at opposite sides of each conductive line, where the conductive line lies over gate oxide. The width of the conductive line at such a region of dopant implant defines the channel length of the formed IGFET transistor.
Within each of the above-described process steps, there are one or more variable physical attributes (or xe2x80x9cprocess parametersxe2x80x9d) that control the final outcome of the produced device. Some process parameters may be adjusted by a line operator. Some are xe2x80x9csetxe2x80x9d by the design of the process equipment that is installed into the mass-production line.
Post-exposure development time and temperature are also subject to variance away from pre-established goal values. The diffusion length of the development chemistry may vary across a wafer. In a subsequent plasma etch, the variables can include: time, pressure, temperature, flow rate, and field-proximity effects resulting from the pitch and step profile of closely-spaced mask features.
Because successive steps of IC production tend to be interdependent, a slight variation in parameter(s) of one process step can be magnified by a further variation in the parameters of a second process step to produce unacceptable numbers of defective product at the output end of the mass-production line.
For example, if PR (photoresist) thicknesses decrease slightly and the focal depth of the exposure optics also decreases slightly and the exposure dosage also decreases slightly during production of a first-sampled IC chip as compared to the corresponding process parameters for a second-sampled IC chip, the combined effect may be to significantly shift the position and intensity of the radiation exposure pattern relative to the photoresist layer during the production of the first-sampled IC chip. The second-sampled IC chip may come off the production line in acceptable form while the first-sampled chip comes out of the same mass-production line in defective form.
It is hard to pinpoint why mass-production yield for a given circuit layout on a given mass-production line becomes unacceptably low. The statistical variance of PR thickness across the production lot may be small. The statistical variance of focus across the production lot may be small. But the physical interaction between the two noise quantities can be such that the overall lithography process produces chips having a much larger variance in terms of critical dimensions. If the overall variance in final critical dimensions becomes too large, production yield may suffer significantly.
The interdependence of variance of a number of specific process steps is not easily perceived. Hence, computer experimentation has aided the engineer by allowing distributions of key output parameters to be estimated. Generally, this is accomplished by varying selected inputs or noise factors, then by running computer code to simulate the variation likely to occur in manufacturing.
Different process analysis and design approaches exist with respect to the description, modeling and modification of a given process based upon the variation likely to occur in the process. The first approach, generally referred to as system design (as defined by Genichi Taguchi in xe2x80x9cIntroduction to Quality Control,xe2x80x9d p.75 (Asian Productivity Organization, 1986)), comprises the general product architecture, schematic, functionality, and feature set. In the second approach, generally referred to as parameter design, as defined by Taguchi, id. at p. 76, nominal process settings are determined in order to minimize performance variability and costs. In a third approach, referred to as tolerance design (Taguchi, id. at p. 78), tolerance and specification limits are determined in order to achieve engineering objectives and minimize costs. The invention described herein is in the tolerance design area.
Computer experiments have emerged as one way engineers can model process designs using statistical methods to devise process parameters for semiconductor manufacturing. The models allow engineers to increase product yields by selecting variances in certain process factors such that the variance(s) of the output characteristic(s) does(do) not adversely affect product performance.
One modeling paradigm involves a description of the effect of a change in one process variation on the output of another relative to some common reference. For the purposes of this description, this paradigm will be defined as an xe2x80x9cengineering process window.xe2x80x9d In one aspect, a process window is the inherent effect of a change in one parameter resulting in an effect on any other parameter which may be plotted in two (or perhaps more) dimensions. Stated still another way, in the case of two input parameters, a process window is any description of the tradeoff between the tolerance of one input parameter and the tolerance of other input parameters. Parameter design gives a process window which defines, as a function of input parameters X1. . . Xf, the region in which the product performs in conformance to specifications. Tolerance design yields, for a given range of input parameters, the tolerances X1xc2x1xcex941, . . . , Xfxc2x1xcex94f which allow the product to perform in conformance to its performance specification.
In computer experimentation involving engineering process windows, calibration to realistic measurements is generally compared with computer-implemented models. Data from the process may be sampled from sacrificial areas of actual processed substrates, with the sample data then used with empirical experiments or computer simulators (such as, for example, the DEPICT photolithography simulator available from Technology Modeling Associates of Palo Alto, Calif.) to provide a calibrated model of the process results.
Process windows which compare results of altering two factors are relatively simple: the model deals with changes to one parameter which affect another parameter. The analysis becomes much more complex where a number of input factors are involved as in, for example, a cross-correlation of device parameters which are utilized in a semiconductor fabrication process and affect conductive line formation. Such factors include, and are abbreviated in this specification as follows:
One descriptive method used. successfully to compute variance parameters is known as analysis of manufacturing variance (AMV) and is set forth in Heavlin, xe2x80x9cVariance Components and Computer Experiments,xe2x80x9d reference paper no. 9, cited above.
In analysis of manufacturing variance, the goal is to decompose the total variance of a process into components, one component associated with each input factor, and consistent with the variation to be anticipated in manufacturing. In a basic form of AMV, each noise factor is perfectly controlled, and the reduction in output variation noted. AMV allows for control of subsets of factors as well.
AMV in its simplest form comprises using Latin hypercube (LHC) sampling for factors X1. . . Xf in a computer simulation, calculating the total variance of the resulting values, and substituting the mean of each factor to calculate the reduction in variance from the total variance to estimate the contributions of the factors held constant. AMV analysis is illustrated in the table shown in FIG. 3A. In FIG. 3A, each xcex represents a noise factor for an input under determination where xcex=0, perfect control (no variance) of the input factor is presumed. One factor per iteration is presumed perfect, and all other factors are allowed to vary.
Another methodology related to AMV is described in U.S. Pat. No 5,646,870 and referred to therein as incremental leveraging. Initially, a predefined goal for variation is selectedxe2x80x94for example 10%xe2x80x94and an evaluation of each factor made on this basis. Process parameters are selected one at a time and the variance of the selected process parameter is temporarily reset to zero. The noisy set of simulations is re-run and the new total variance is calculated and stored while still retaining the variance value of an original first run where none of the relevant variances were reset to zero.
Incremental leveraging has the advantage that it is good at suggesting one solution for input tolerance design. It does not, however, provide a mechanism for flexibility in allowing more than the one solution it provides for changing the tolerance constraints of the factors in the process under consideration.
In co-pending application Ser. No. 09/130,528, entitled Statistically Based Process Windows, inventor William D. Heavlin, assigned to the assignee of the present application, incremental leveraging methodology is utilized as a basis to define a statistically-based, process window algorithm wherein the response variability of a process is represented as a function of the tolerances of each variable. In brief, one utilizes the tolerance variations defined in the aforementioned algorithms as inputs to determine, for any number of process variables, the effect of varying the tolerance of each factor on the tolerances of other factors under consideration relative to a response factor for the entire process. This algorithm may be performed in a computer and have an output provided to a process engineer who may then determine optimal modifications to the nominal process under consideration to derive a toleranced process.
In general, the method defined in co-pending application Ser. No. 09/130,528 comprises: defining a nominal process; evaluating F input factors {Xf:f=1, . . . , F} which affect the output of the nominal process; and defining, as a result of the evaluation, a toleranced process having an output response less susceptible to variance in the input factors. The evaluation is performed by representing the variability of the response of the process as a function of the factors"" current variability and selected tightening factors; performing an evaluation where the tightening factors are varied using an orthogonal array, varying the factors over [0,1]F; and modeling, using kriging interpolation, a neural network or equivalents, to determine moments or other statistics of a distribution of the process for given changes in the constraints of each factor.
The method of forming the semiconductor device in accordance with the present invention results in better planning of next-generation equipment requirements and ultimately in improved product yields as the considered factors are improved upon.
An objective of the invention is to allow process engineers to determine, on a lot-by-lot basis, whether and how to make improvements in the processing of the particular lot under consideration.
A further objective of the present invention is to provide an evaluation method for process engineers to make qualitative judgements about the manufacturability of certain processes based on models of the output given a variety of inputs to the process.
Yet another object of the invention is to improve yields in multi-faceted manufacturing processes, and particularly semiconductor manufacturing applications.
In one aspect, the invention, roughly described, comprises a method of fabricating a multi-component semiconductor device assembly, comprising: defining a nominal semiconductor manufacturing process having a plurality of process steps, the nominal process including a number of process input factors X1xe2x88x92XF which, when perfectly controlled to meet the nominal process settings for such factors, produce a device assembly with defined operating characteristics: performing at least one of said plurality of process steps on at least one lot of wafers; and evaluating the process by: (1) representing the variability of the response of the operating characteristic as a function of the actual variability of at least one of said factors and at least one tightening factor; (2) evaluating said input factors subject to a variety of tightening factors array over [0,1]F; and (3) modeling the output using an interpolation function to determine suitable tolerance models impacting control of one or more of said input factors.